Smart Lift Controller System
Intelligent elevator control system in Verilog with optimized scheduling for multi-floor buildings.
- Role: Developer
- Timeline: November 2020
- Team: Computer Architecture Lab (2 members)
- Technologies: Verilog, Logic Design, Simulation, Algorithms
- Link: https://github.com/Laxman824/COL215-COMP-ARCH-assignments
Problem
Computer Architecture lab: design a digital system using Verilog. Elevator controller chosen for its state machine complexity and real-world applicability.
Solution
Designed a 3-floor elevator controller with optimized scheduling (SCAN algorithm), direction priority, door timing, emergency stop, and LED/seven-segment display output.
Impact
- Efficient SCAN scheduling algorithm
- Minimal wait time optimization
- Complete state machine implementation
- Synthesizable on FPGA
Key features
- 3-floor elevator simulation
- SCAN scheduling algorithm
- Direction priority handling
- Door open/close timing
- Emergency stop functionality
- Floor indicator display
- Request queue management
- Overload detection
Tech stack
- Hdl: Verilog
- Simulation: ModelSim, Vivado
- Fpga: Xilinx Artix-7
- Tools: GTKWave
What K Laxman learned
- Finite State Machine design
- Verilog HDL programming
- Digital logic optimization
- FPGA synthesis constraints
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